A ratio-independent algorithmic analog-to-digital conversion technique

An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.

[1]  T. Hornak,et al.  A high precision component-tolerant ADC , 1975 .

[2]  W. Black,et al.  An algorithmic analog-to-digital converter , 1977, 1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  H.J. De Man,et al.  An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling , 1980, IEEE Journal of Solid-State Circuits.

[4]  R. Webb,et al.  A 12b A/D converter , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[5]  P. Gray,et al.  A low-noise chopper-stabilized differential switched-capacitor filtering technique , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  J. Doernberg,et al.  Full-speed testing of A/D converters , 1984 .

[7]  Chenming Hu,et al.  Switch-induced error voltage on a switched capacitor , 1984 .

[8]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.