An 180 nm CMOS 1.84-to-3.62 GHz fractional-N frequency synthesizer with skewed-reset PFD for removing noise-folding effect
暂无分享,去创建一个
[1] Hao Min,et al. A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[2] Tsung-Hsien Lin,et al. A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[3] K.J. Wang,et al. Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL , 2008, IEEE Journal of Solid-State Circuits.
[4] Jie Liu,et al. A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[5] O. Kobayashi,et al. A 0.3mm2 90-to-770MHz fractional-N Synthesizer for a digital TV tuner , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).