ℰℱect olerant layout synthesis
暂无分享,去创建一个
[1] C. D. Gelatt,et al. Optimization by Simulated Annealing , 1983, Science.
[2] C.H. Stapper,et al. Integrated circuit yield statistics , 1983, Proceedings of the IEEE.
[3] G. A. Allan,et al. A yield improvement technique for IC layout using local design rules , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Jose Pineda de Gyvez. Integrated circuit defect-sensitivity - theory and computational models , 1993, The Kluwer international series in engineering and computer science.
[5] Israel Koren,et al. Yield Models for Defect-Tolerant VLSI Circuits: A Review , 1989 .
[6] Wojciech Maly,et al. Computer-aided design for VLSI circuit manufacturability , 1990, Proc. IEEE.
[7] Israel Koren,et al. New routing and compaction strategies for yield enhancement , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
[8] A. V. Ferris-Prabhu,et al. Defects, Faults and Semiconductor Device Yield , 1989 .
[9] W Stephen. OPTIMIZATION OF PARAMETRIC YIELD , 1991 .
[10] T. Ohtsuki,et al. Recent advances in VLSI layout , 1990, Proc. IEEE.
[11] Israel Koren,et al. Fault tolerance in VLSI circuits , 1990, Computer.
[12] Takeshi Yoshimura,et al. Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Paul D. Franzon,et al. A Layout-Driven Yield Predictor and Fault Generator , 1993 .
[14] Ron Y. Pinter,et al. Channel Routing for Integrated Circuits , 1990 .
[15] Suchai Thanawastien,et al. DTR: A Defect-Tolerant Routing Algorithm , 1989, 26th ACM/IEEE Design Automation Conference.