Employing optimal experimental design to optimize the accelerated life test plan for TDDB
暂无分享,去创建一个
[1] Akira Toriumi,et al. Re-consideration of influence of silicon wafer surface orientation on gate oxide reliability from TDDB statistics point of view , 2010, 2010 IEEE International Reliability Physics Symposium.
[3] Huairui Guo,et al. D-optimal reliability test design for two-stress accelerated life tests , 2007, 2007 IEEE International Conference on Industrial Engineering and Engineering Management.
[4] J. McPherson,et al. Acceleration Factors for Thin Gate Oxide Stressing , 1985, 23rd International Reliability Physics Symposium.
[5] W. Meeker. A Comparison of Accelerated Life Test Plans for Weibull and Lognormal Distributions and Type I Censoring , 1984 .
[6] Xiaobo Ma,et al. Optimal thermal design of a high power package using the design of experiment (DOE) , 2012 .
[7] M.K. Othman,et al. Design Of Experiment (DOE) For Thickness Reduction Of GaAs Wafer Using Lapping Process , 2006, 2006 IEEE International Conference on Semiconductor Electronics.
[8] M.T.M. Gouh,et al. Design and Optimization of 40V, 0.18μm versatile HVL-DMOS device with DOE , 2008, 2008 IEEE International Conference on Semiconductor Electronics.
[11] William Q. Meeker,et al. Optimum Accelerated Life-Tests for the Weibull and Extreme Value Distributions , 1975, IEEE Transactions on Reliability.
[12] H. Iwai,et al. Estimation of process variation impact on DG-FinFET device performance using Plackett-Burman design of experiment method , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.
[13] W. Choi,et al. Prediction of TDDB characteristics under constant current stresses , 1996 .
[14] Tao Yang,et al. A Novel Approach to Optimal Accelerated Life Test Planning With Interval Censoring , 2013, IEEE Transactions on Reliability.
[15] Yu Gu,et al. Drop test simulation and DOE analysis for design optimization of microelectronics packages , 2006, 56th Electronic Components and Technology Conference 2006.
[16] Cao Li,et al. Dimension optimization of through silicon via(TSV) through simulation and design of experiment (DOE) , 2012 .
[17] R. Pan,et al. Generating optimal design for ALT experiment with time censoring , 2013, 2013 Proceedings Annual Reliability and Maintainability Symposium (RAMS).