Coordinating 3D designs: Interface IP, standards or free form?

Three dimensional integration technology introduces new complexities to design and particularly codesign. Additional complexity is added when one considers that the design needs to be “future-proof”. How do you ensure that the 3D chip stack will work for future chips within the stack, whose parameters are yet to be fully anticipated. This paper proposes that this be managed through an Interface IP approach Design blocks with associated properties that not only supports signaling and power delivery but also constraints that must be managed between chips both during design but also in-situ and as part of physical verification.