Analyzing Reliability and Performance Trade-Offs of HLS-Based Designs in SRAM-Based FPGAs Under Soft Errors

The increasing system complexity of FPGA-based hardware designs and shortening of time-to-market have motivated the adoption of new designing methodologies focused on addressing the current need for high-performance circuits. High-Level Synthesis (HLS) tools can generate Register Transfer Level (RTL) designs from high-level software programming languages. These tools have evolved significantly in recent years, providing optimized RTL designs, which can serve the needs of safety-critical applications that require both high performance and high reliability levels. However, a reliability evaluation of HLS-based designs under soft errors has not yet been presented. In this work, the trade-offs of different HLS-based designs in terms of reliability, resource utilization, and performance are investigated by analyzing their behavior under soft errors and comparing them to a standard processor-based implementation in an SRAM-based FPGA. Results obtained from fault injection campaigns and radiation experiments show that it is possible to increase the performance of a processor-based system up to 5,000 times by changing its architecture with a small impact in the cross section (increasing up to 8 times), and still increasing the Mean Workload Between Failures (MWBF) of the system.

[1]  Hiroyuki Tomiyama,et al.  CHStone: A benchmark program suite for practical C-based high-level synthesis , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[2]  Luigi Carro,et al.  Impact of GPUs Parallelism Management on Safety-Critical and HPC Applications Reliability , 2014, 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks.

[3]  Fernanda Gusmão de Lima Kastensmidt,et al.  Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors , 2016, ARC.

[4]  Robert J. Halstead,et al.  High-Level Language Tools for Reconfigurable Computing , 2015, Proceedings of the IEEE.

[5]  R. Velazco,et al.  Combining Results of Accelerated Radiation Tests and Fault Injections to Predict the Error Rate of an Application Implemented in SRAM-Based FPGAs , 2010, IEEE Transactions on Nuclear Science.

[6]  Robert Carlson,et al.  Towards a generic and adaptive System-on-Chip controller for space exploration instrumentation , 2015, 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS).

[7]  M. Husejko,et al.  Investigation of High-Level Synthesis tools’ applicability to data acquisition systems design based on the CMS ECAL Data Concentrator Card example , 2015 .

[8]  Muhammad Shafique,et al.  Reliable Software for Unreliable Hardware - A Cross Layer Perspective , 2016 .

[9]  L. E. Seixas,et al.  Experimental setup for Single Event Effects at the São Paulo 8UD Pelletron Accelerator , 2014 .

[10]  Yu Ting Chen,et al.  A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Michael J. Wirthlin,et al.  High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond , 2015, Proceedings of the IEEE.

[12]  Heather Quinn,et al.  A Method and Case Study on Identifying Physically Adjacent Multiple-Cell Upsets Using 28-nm, Interleaved and SECDED-Protected Arrays , 2014, IEEE Transactions on Nuclear Science.

[13]  Jason Helge Anderson,et al.  LegUp: high-level synthesis for FPGA-based processor/accelerator systems , 2011, FPGA '11.