High Level Power Estimation Models for FPGAs

This paper presents a high level power estimation methodology for the FPGA-based designs. The high level estimation techniques are usually targeted towards ASIC designs. We evaluate the applicability of these techniques for FPGAs. The current techniques give a separate power estimation model for each IP. Instead, our method aims to develop a common power model for multiple IPs. This is made possible by the structured nature of FPGA fabrics having fixed resources -- LUTs, multipliers, BRAMs, etc. We developed a statistical learning based approach that includes the effect of design specific information as well as FPGA resource utilization information. The work demonstrates the effect of varying the activity-factor of the design and the FPGA resources consumption on dynamic power, using a set of 13 IPs as benchmarks. We also study the effect of statistical clustering technique on the model accuracy. The average percentage error in the model stayed around 4%for activity-factor variation and around 6% for resource-utilization variation.