Soft error rate estimation of combinational circuits based on vulnerability analysis

Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a novel approach is proposed for SER estimation of combinational circuits based on vulnerability analysis. The authors introduce a concept called probabilistic vulnerability window (PVW) which is an inference of necessary conditions for a single event transient (SET) to cause observable errors in the circuit. A proposed computational framework calculates PVWs for all circuit gates in a backward-traversing algorithm enabling the circuit designers for an accurate and efficient SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it is applied for estimating the SER considering various different SET widths while runtime of traditional estimation methods increases in such cases. In addition, results verify the accuracy (average difference of 0.02) and speedup (about four orders of magnitude) of the proposed method when compared with the Monte Carlo-based fault injection simulation on ISCAS'85 benchmark circuits.

[1]  R. K. Shyamasundar,et al.  Introduction to algorithms , 1996 .

[2]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[3]  Soft-Error-Rate-Analysis (SERA) Methodology , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Robert Baumann,et al.  Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.

[5]  John P. Hayes,et al.  Accurate reliability evaluation and enhancement via probabilistic transfer matrices , 2005, Design, Automation and Test in Europe.

[6]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[7]  Bin Zhang,et al.  FASER: fast analysis of soft error susceptibility for cell-based designs , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[8]  Narayanan Vijaykrishnan,et al.  SEAT-LA: a soft error analysis tool for combinational logic , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[9]  Diana Marculescu,et al.  Circuit Reliability Analysis Using Symbolic Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Yuan Xie,et al.  Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[11]  B. Narasimham,et al.  Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.

[12]  David Blaauw,et al.  Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Massoud Pedram,et al.  Probabilistic error propagation in logic circuits using the Boolean difference calculus , 2008, 2008 IEEE International Conference on Computer Design.

[14]  Abhijit Chatterjee,et al.  Accurate Linear Model for SET Critical Charge Estimation , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  John P. Hayes,et al.  Signature-Based SER Analysis and Design of Logic Circuits , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Mehdi Baradaran Tahoori,et al.  Soft error modeling and remediation techniques in ASIC designs , 2010, Microelectron. J..

[17]  Charles H.-P. Wen,et al.  Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

[18]  peixiong zhao,et al.  Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes , 2010, IEEE Transactions on Nuclear Science.

[19]  Alan Wood,et al.  The impact of new technology on soft error rates , 2011, 2011 International Reliability Physics Symposium.

[20]  Cecilia Metra,et al.  Impact of Aging Phenomena on Soft Error Susceptibility , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

[21]  J. Segura,et al.  Analytical Modeling of Single Event Transients Propagation in Combinational Logic Gates , 2012, IEEE Transactions on Nuclear Science.

[22]  Mehdi Baradaran Tahoori,et al.  Efficient algorithms to accurately compute derating factors of digital circuits , 2012, Microelectron. Reliab..

[23]  T. D. Loveless,et al.  Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions , 2013, IEEE Transactions on Nuclear Science.

[24]  Charles H.-P. Wen,et al.  Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection , 2013, IEEE Design & Test.

[25]  Dan Alexandrescu,et al.  A Practical Approach to Single Event Transient Analysis for Highly Complex Design , 2013, J. Electron. Test..

[26]  Charles H.-P. Wen,et al.  CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[27]  Adrian Evans,et al.  Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[28]  D. Rajan.  Probability, Random Variables, and Stochastic Processes , 2017 .