A 65nm CMOS high-IF superheterodyne receiver with a High-Q complex BPF

We propose a highly reconfigurable superheterodyne receiver that employs a 3rd-order complex IQ charge-sharing band-pass filter (BPF) for image rejection and 1st-order feedback based RF-BPF for channel selection filtering. The operating RF input frequency of the receiver is 500 MHz-1.2 GHz with varying high-IF range of 33-80 MHz. All the gain stages are merely inverter-based gm stages. The total gain of the receiver is 35dB and in-band IIP3 at midgain is +10 dBm. The NF of the receiver is 6.7dB, which is acceptable for the receiver without an LNA. The architecture is highly reconfigurable and follows the technology scaling. The RX occupies 0.47 mm2 of active area and consumes 24.5 mA at 1.2V power supply.

[1]  Ahmad Mirzaei,et al.  A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE , 2011, IEEE Journal of Solid-State Circuits.

[2]  Eric A. M. Klumperink,et al.  8-Path tunable RF notch filters for blocker suppression , 2012, 2012 IEEE International Solid-State Circuits Conference.

[3]  H. Darabi,et al.  A Blocker Filtering Technique for SAW-Less Wireless Receivers , 2007, IEEE Journal of Solid-State Circuits.

[4]  Ahmad Mirzaei,et al.  A low-power process-scalable superheterodyne receiver with integrated high-Q filters , 2011, 2011 IEEE International Solid-State Circuits Conference.

[5]  J. Kostamovaara,et al.  A quadrature charge-domain sampler with embedded FIR and IIR filtering functions , 2006, IEEE Journal of Solid-State Circuits.