Multilevel Based Global Routing Algorithm for Hierarchical FPGA

This paper presents an efficient global routing algorithm for a hierarchical interconnection architecture of FPGA. What is different from the traditional FPGA routing algorithm is that the proposed algorithm takes advantage of the hierarchical structure of this particular FPGA. We use a hierarchical tree as the routing resource representation of the corresponding interconnection architecture. In the routing phase, the global routing problem for each net is represented as a sub-tree determination problem. As soon as the location of each Logic Block is fixed, we can use a tree-growth-like algorithm to determine the sub-tree on the corresponding routing resource tree. The algorithm is very efficient and fast since the sub-tree is determined once we determined the position of each Logic Block. On the other hand, we can use this method to evaluate the routability of the corresponding placement results.

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