Radiation Testing Complementary (Symmetry) Metal Oxide Semi-Conductor (CMOS) Arrays for Satellites
暂无分享,去创建一个
Considerable interest has been generated in the radiation tolerance of certain classes of semiconductor devices that are currently programmed for flight on various Air Force satellites. This interest was initiated by a re-evaluation of the geomagnetically trapped charged particle fluences that indicate greater radiation exposure during the disturbed or active periods of the solar cycle.1 Also the ever increasing complexity and hence the sensitivity of integrated circuits that are planned for use in computers and data processing systems on board satellites has created an urgent need to precisely determine the operational lifetimes of these devices during radiation exposures. In order to assess the flight worthiness of the devices the Air Force Weapons Laboratory and the Air Force Space and Missile Systems Organization conducted a cooperative effort to test a large number of different types of satellite semiconductors during 1975-1977. The evaluation effort examined various complementary symmetry metal oxide (CMOS) medium and large scale integrated circuits.
[1] B. L. Gregory,et al. Process Optimization of Radiation-Hardened CMOS Integrated Circuits , 1975, IEEE Transactions on Nuclear Science.
[2] J. Janni,et al. Degradation of Satellite Electronics Produced by Energetic Electrons , 1977 .
[3] C. W. Gwyn,et al. Radiation Failure Modes in CMOS Integrated Circuits , 1973 .