Incremental diagnosis of multiple open-interconnects
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[1] Masahiro Fujita,et al. Modeling the unknown! Towards model-independent fault and error diagnosis , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[2] Srikanth Venkataraman,et al. Poirot: Applications of a Logic Fault Diagnosis Tool , 2001, IEEE Des. Test Comput..
[3] Elizabeth M. Rudnick,et al. Bridge fault diagnosis using stuck-at fault simulation , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Vishwani D. Agrawal,et al. Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.
[5] F. Joel Ferguson,et al. Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] I. Pomeranz,et al. On testing of interconnect open defects in combinational logic circuits with stems of large fanout , 2002, Proceedings. International Test Conference.
[7] W. Kent Fuchs,et al. A deductive technique for diagnosis of bridging faults , 1997, ICCAD 1997.
[8] Haluk Konuk. Fault simulation of interconnect opens in digital CMOS circuits , 1997, ICCAD 1997.
[9] Magdy S. Abadir,et al. Efficient and Exact Diagnosis of Multiple Stuck-At Faults , 2002 .
[10] Michael S. Hsiao,et al. On efficient error diagnosis of digital circuits , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[11] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[12] Janak H. Patel,et al. New Techniques for Deterministic Test Pattern Generation , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[13] Jochen A. G. Jess,et al. On accurate modeling and efficient simulation of CMOS opens , 1993, Proceedings of IEEE International Test Conference - (ITC).
[14] Antonio Rubio,et al. Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Tracy Larrabee,et al. Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis , 1996, Proceedings International Test Conference 1996. Test and Design Validity.
[16] Andreas G. Veneris,et al. Incremental diagnosis and correction of multiple faults and errors , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[17] Ibrahim N. Hajj,et al. Design error diagnosis and correction via test vector simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Srikanth Venkataraman,et al. A technique for logic fault diagnosis of interconnect open defects , 2000, Proceedings 18th IEEE VLSI Test Symposium.
[19] Shi-Yu Huang,et al. ErrorTracer: design error diagnosis based on fault simulation techniques , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[20] Robert K. Brayton,et al. Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.