Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
暂无分享,去创建一个
[1] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[2] Axel Jantsch,et al. Methods for fault tolerance in networks-on-chip , 2013, CSUR.
[3] Juha Plosila,et al. Network on Chip Routing Algorithms , 2006 .
[4] Minu Mathew,et al. Reconfigurable router design for Network-on-Chip , 2014, 2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014].
[5] Sao-Jie Chen,et al. Networks on Chips: Structure and Design Methodologies , 2012, J. Electr. Comput. Eng..
[6] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[7] Ashish Sharma,et al. Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration , 2014, TRETS.
[8] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[9] Santanu Chattopadhyay,et al. Network-on-chip architecture design based on mesh-of-tree deterministic routing topology , 2008, Int. J. High Perform. Syst. Archit..
[10] Alain Greiner,et al. A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip , 2008, 2008 45th ACM/IEEE Design Automation Conference.