论文信息 - Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structures for high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V/sub th/ lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V/sub th/ lowering at 0.4- mu m gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4- mu m gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4- mu m gate length. >

[1] S. M. Sze,et al. Physics of semiconductor devices , 1969 .

[2] Eiji Takeda,et al. Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI , 1988 .

[4] S. Ogura,et al. Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor , 1980 .

[5] G. Baccarani,et al. Generalized scaling theory and its application to a ¼ micrometer MOSFET design , 1984, IEEE Transactions on Electron Devices.

[6] R.R. Troutman,et al. VLSI limitations from drain-induced barrier lowering , 1979, IEEE Transactions on Electron Devices.

[7] M. Mock. On heavy doping effects and the injection efficiency of silicon transistors , 1974 .

[8] E. Takeda,et al. Constraints on the application of 0.5-µm MOSFET's to ULSI systems , 1985, IEEE Transactions on Electron Devices.

[9] D. Kern,et al. High transconductance and velocity overshoot in NMOS devices at the 0.1- mu m gate-length level , 1988, IEEE Electron Device Letters.

[10] S. Asai,et al. Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis , 1979, IEEE Journal of Solid-State Circuits.