A fast testing method for sequential circuits at the state transition level

In this paper an efficient method called the fast augmented state transition (FAST) test method is proposed to alleviate the testing problem of sequential circuits at the state transition level. By adding some extra logic gates to a sequential circuit under test the FAST method guarantees that each state of the augmented circuit has both the shortest distinguishing and synchronizing sequences, hence the testing complexity can be greatly reduced. The test length of the FAST method is shorter than any other exhaustive testing approaches based on the state transition level. Furthermore the test set for the augmented circuit can be easily identified.

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