Research and Implementation of the Multi-Channel Cell Reassemble Technology

Multi-channel cell reassembly is a kind of typical technology for buffer management in network equipment which is widely used in ATM interfaces and the design of crossbar switches. This paper presents a multi-channel cell reassembly and scheduling algorithm based on the shared-memory structure. Theoretical analysis show that the structure has fewer volume demand of the buffer and determinate reassembly delay bound. Finally, we introduce the implementation of this structure using FPGA, and apply it to the ATM interface design of core routers successfully.