Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

This paper presents a new detailed analysis of low-voltage differential signaling (LVDS) output buffers that are intended for use in high-speed integrated circuits. Three theoretically possible architectures of a LVDS output driver are discussed in rigorous detail, resulting in the recognition of the most power-conserving circuit configuration. An innovative realization of this identified low-power architecture is presented in this paper along with computer simulation results and test lab measurement data. The novel LVDS driver is designed using a unique hetero-junction bipolar transistor structure. Computer simulation results show total current consumption of 6.3 mA for the bipolar driver at a 1-GHz clock frequency while operating from a positive supply voltage between 1.7 and 3.3 V, as well as demonstrate full stage compliance with all the requirements of the IEEE 1596.3-1996 standard. The presented version of the buffer was utilized in a multiplexer/demultiplexer chip set that was fabricated in a modern 50-GHz-fT SiGe technology. Test results of the LVDS output buffer taken from five different chip samples reveal high-quality output eyes with more than 0.99 UI opening and close matching between the measured parameters and simulation results

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