Fast Charge Pump Phase Locked Loop with a BBFC: A Numerical Confirmation

Speeding up a synthesizer's locking process can be considered as speeding up the charge pump PLL. Several methods have been introduced to increase the speed of the locking process. One way to achieve fast locking is to use a bang- bang frequency comparator (BBFC) in the feed-trough path to achieve a faster locking process. In this paper, we present a differential equation for this fast CPPLL which shows how the BBFC can decrease the settling time in a charge pump PLL. Simulations in MATLAB are confirmed by a differential equation solved in Maple using a numerical method. Using the extracted equation and solving it by numerical method we can predict the system's behavior.

[1]  Yin Shi,et al.  Fast locking and high accurate current matching phase-locked loop , 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

[2]  Hossein Miar Naimi,et al.  A fast synthesizer using a bang-bang frequency comparator and locking status indicator , 2011, Proceedings of the 2011 International Conference on Electrical Engineering and Informatics.

[3]  Robert M. Corless,et al.  Initial value problems for ODEs in problem solving environments , 2000 .

[4]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .

[5]  G. Baudoin,et al.  Analysis of a PLL based frequency synthesizer using switched loop bandwidth for Mobile WiMAX , 2008, 2008 18th International Conference Radioelektronika.