A 300Mb/s clock recovery and data retiming system

A single bipolar chip housed with a Surface Acoustic Wave filter in a multi-cavity ceramic DIP to provide clock recovery and data retiming up to 300Mb/s will be discussed. Device accepts a jittered data input and provides a low jitter clock (<3°rms)and retimed data with 10% eye width closure on ECL balanced outputs.

[1]  R. Paski,et al.  A regenerator chip set for high speed digital transmission , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.