Minimizing power under performance constraint
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[1] Yuan Taur,et al. CMOS design near the limit of scaling , 2002 .
[2] Louise Trevillyan,et al. An integrated environment for technology closure of deep-submicron IC designs , 2004, IEEE Design & Test of Computers.
[3] Dennis Sylvester,et al. Pushing ASIC performance in a power envelope , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[4] Chingwei Yeh,et al. Layout techniques supporting the use of dual supply voltages for cell-based designs , 1999, DAC '99.
[5] Daniel Brand,et al. BooleDozer: Logic synthesis for ASICs , 1996, IBM J. Res. Dev..
[6] Mark Horowitz,et al. Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.
[7] Suhwan Kim,et al. Low-power circuits and technology for wireless digital systems , 2003, IBM J. Res. Dev..
[8] Leon Stok,et al. Combinatorial cell design for CMOS libraries , 2000, Integr..