Dataflow Analysis and Optimization of High Level Language Code for Hardware-Software Co-Design

(ABSTRACT) Recent advancements in FPGA technology have provided devices which are not only suited for digital logic prototyping, but also are capable of implementing complex computations. The use of these devices in multi-FPGA Custom Computing Machines (CCMs) has provided the potential to execute large sections of programs entirely in custom hardware which can provide a substantial speedup over execution in a general-purpose sequential processor. Unfortunately, the development tools currently available for CCMs do not allow users to easily configure multi-FPGA platforms. In order to exploit the capabilities of such an architecture, a procedure has been developed to perform a dataflow analysis of programs written in C which is capable of several hardware-specific optimizations. This, together with other software tools developed for this purpose, allows CCMs and their host processors to be targeted from the same high-level specification. ACKNOWLEDGEMENTS I would like to thank Dr. Peter Athanas for his constant encouragement throughout the duration of this project. I would also like to thank Dr. Abbott and Dr. Davis for their support and for their time. I would like to thank Jim Peterson for his help throughout this project. I would also like to thank my family for their consistent support throughout my academic career. In addition I would like to thank all of my friends for their continued support. Finally, a special thanks to my sister, Amalie, who has consistently encouraged me to do my best.

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