Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks

Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a scan structure. Additionally, scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of scan chains. Therefore, scan-chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional scan-chain diagnosis. Therefore, this article proposes a novel scan-chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing scan-chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed scan-chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.

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