A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator

This paper describes a 0.35-/spl mu/m CMOS fourth-order bandpass analog-digital sigma-delta (/spl Sigma//spl Delta/) modulator for wide-band base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The /spl Sigma//spl Delta/ modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 mm/sup 2/ of silicon area.

[1]  W. M. Snelgrove,et al.  A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator , 1998 .

[2]  Pieter Rombouts,et al.  A study of dynamic element-matching techniques for 3-level unit elements , 2000 .

[3]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[4]  Zhongnong Jiang,et al.  A 16-bit, 5MHz multi-bit sigma-delta ADC using adaptively randomized DWA , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[5]  Marcello Donati,et al.  The Software Radio Technique Applied to the RF Front-end for Cellular Mobile Systems , 2001 .

[6]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[7]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[8]  A. Wiesbauer,et al.  A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13/spl mu/m CMOS , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[9]  Jesper Steensgaard,et al.  Bootstrapped low-voltage analog switches , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[10]  Saska Lindfors,et al.  A Dual-Mode 80MHz Bandpass DS-Modulator for a GSW/WCDMA IF-receiver , 2002 .

[11]  Franco Maloberti,et al.  Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Franco Maloberti,et al.  Use of dynamic element matching in a multi-path sigma-delta modulator , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[13]  V.S.L. Cheung,et al.  A 3.3-V 240-MS/s CMOS bandpass /spl Sigma//spl Delta/ modulator using a fast-settling double-sampling SC filter , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[14]  F. Maloberti,et al.  A mirror image free two-path bandpass /spl Sigma//spl Delta/ modulator with 72 dB SNR and 86 dB SFDR , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[15]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[16]  W. Sansen,et al.  A 3.3 V 15-bit delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL-applications , 1999, Proceedings of the 24th European Solid-State Circuits Conference.

[17]  Hai Tao,et al.  Data converters for communication systems , 1998 .

[18]  R. Schreier,et al.  Noise-shaped multbit D/A convertor employing unit elements , 1995 .