Testing of Vega2, a chip multi-processor with spare processors.

Vega2 is a CMP (chip multi-processor) with 48 processor cores, and several spare cores to improve yield. The chip also contains about 1000 memory macros both inside and outside the processor cores. The larger memories have column redundancy as well. The main DFT challenge for Vega2 is to produce an architecture that makes it easy to identify defective processors, thoroughly test the memories and efficiently apply ATPG patterns.

[1]  Chasing subtle embedded RAM defects for nanometer technologies , 2005, IEEE International Conference on Test, 2005..

[2]  Mack W. Riley,et al.  Testability features of the first-generation CELL processor , 2005, IEEE International Conference on Test, 2005..

[3]  Janak H. Patel,et al.  Reducing test application time for built-in-self-test test pattern generators , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[4]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Zaid Al-Ars,et al.  Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests , 2003, J. Electron. Test..

[6]  Nilanjan Mukherjee,et al.  X-Press Compactor for 1000x Reduction of Test Data , 2006, 2006 IEEE International Test Conference.

[7]  Amitava Majumdar,et al.  A scalable, low cost design-for-test architecture for UltraSPARC/spl trade/ chip multi-processors , 2002, Proceedings. International Test Conference.

[8]  Shianling Wu,et al.  UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction , 2005, IEEE International Conference on Test, 2005..

[9]  Ad J. van de Goor An Industrial Evaluation of DRAM Tests , 2004, IEEE Des. Test Comput..

[10]  Janak H. Patel,et al.  Reducing test application time for full scan embedded cores , 1999, Digest of Papers. Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352).

[11]  Tung Le,et al.  Testing of UltraSPARC T1 Microprocessor and its Challenges , 2006, 2006 IEEE International Test Conference.