DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

Placement for very-large-scale integrated (VLSI) circuits is one of the most important steps for design closure. We propose a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural network. Implemented on top of a widely-adopted deep learning toolkit PyTorch, with customized key kernels for wirelength and density computations, DREAMPlace can achieve around 40× speedup in global placement without quality degradation compared to the state-of-the-art multi-threaded placer RePlAce. We believe this work shall open up new directions for revisiting classical EDA problems with advancements in AI hardware and software.

[1]  Yao-Wen Chang,et al.  Generalized Augmented Lagrangian and Its Applications to VLSI Global Placement* , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[2]  Tao Lin,et al.  POLAR 3.0: An ultrafast global placement engine , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[3]  Ulf Schlichtmann,et al.  Abacus: fast legalization of standard cell circuits with minimal movement , 2008, ISPD '08.

[4]  David Z. Pan,et al.  elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  David Z. Pan,et al.  DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[6]  Yao-Wen Chang,et al.  NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Chung-Kuan Cheng,et al.  ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  J. Makhoul.  A fast cosine transform in one and two dimensions , 1980 .

[9]  Yao-Wen Chang,et al.  TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Jason Cong,et al.  Parallel multi-level analytical global placement on graphics processing units , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[11]  Ismail Bustany,et al.  POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Martin D. F. Wong,et al.  Accelerate analytical placement with GPU: A generic approach , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Yao-Wen Chang,et al.  TSV-aware analytical placement for 3D IC designs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[14]  David Z. Pan,et al.  GDP: GPU accelerated Detailed Placement , 2018, 2018 IEEE High Performance extreme Computing Conference (HPEC).

[15]  Ismail Bustany,et al.  POLAR: Placement based on novel rough legalization and refinement , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[16]  Andrew B. Kahng,et al.  A faster implementation of APlace , 2006, ISPD '06.

[17]  Jason Cong,et al.  Multilevel generalized force-directed method for circuit placement , 2005, ISPD '05.

[18]  Yao-Wen Chang,et al.  NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  Tao Huang,et al.  Ripple: A Robust and Effective Routability-Driven Placer , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Natalia Gimelshein,et al.  PyTorch: An Imperative Style, High-Performance Deep Learning Library , 2019, NeurIPS.

[21]  Andrew B. Kahng,et al.  RePlAce: Advancing Solution Quality and Routability Validation in Global Placement , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[22]  Adair Dingle.  Fundamentals of Sequential and Parallel Algorithms , 1998, Scalable Comput. Pract. Exp..

[23]  Chung-Kuan Cheng,et al.  ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method , 2015, TODE.

[24]  Andrew B. Kahng,et al.  Architecture and details of a high quality, large-scale analytical placer , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[25]  Jimmy Ba,et al.  Adam: A Method for Stochastic Optimization , 2014, ICLR.

[26]  Yih-Lang Li,et al.  NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Dongjin Lee,et al.  SimPL: An Effective Placement Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  Li Shen,et al.  A Sufficient Condition for Convergences of Adam and RMSProp , 2018, 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR).

[29]  Joseph R. Shinnerl,et al.  mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control , 2007, Modern Circuit Placement.

[30]  Andrew B. Kahng,et al.  An analytic placer for mixed-size placement and timing-driven placement , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[31]  Igor L. Markov,et al.  MAPLE: multilevel adaptive placement for mixed-size designs , 2012, ISPD '12.

[32]  Vaughn Betz,et al.  High-quality, deterministic parallel placement for FPGAs on commodity hardware , 2008, FPGA '08.

[33]  Meng Li,et al.  UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper) , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[34]  Gi-Joon Nam,et al.  The ISPD2005 placement contest and benchmark suite , 2005, ISPD '05.

[35]  David Z. Pan,et al.  ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[36]  Chris C. N. Chu,et al.  FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control , 2007, 2007 Asia and South Pacific Design Automation Conference.