A Feedback-Friendly Large-Scale Clocking Scheme for Adiabatic Quantum-Flux-Parametron Logic Datapaths

Adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic family. Since AQFP gates are powered and clocked by ac excitation current, it is difficult to make feedback loops in datapaths at high clock frequencies, which should be solved in order to design large-scale digital circuits such as microprocessors. In this paper, we propose a novel clocking scheme, which we designate as hybrid clocking, to make feedback loops in AQFP datapaths at high clock frequencies. In hybrid clocking, an entire datapath is divided into two parts: the concurrent-flow block and the counter-flow block. In this way, clock skews are avoided, so that feedback closure can be made independent of clock frequencies. We conduct the simulation of an AQFP buffer chain adopting hybrid clocking at 5 GHz to demonstrate that feedback can be made at high clock frequencies. Then, we investigate the maximum allowable clock skew between AQFP gates using this approach, which is important for physical layout design. We find that, with some modifications to the amplitude of excitation current, the maximum allowable clock skew of 47 ps is achieved at 5 GHz. This large allowable clock skew ensures that hybrid clocking can be adopted in large-scale AQFP datapaths.