A 4-Kb 667-MHz CMOS SRAM using dynamic threshold voltage wordline transistors

The design of a prototypical 667 MHz CMOS 6-T SRAM is presented. A TSMC (Taiwan Semiconductor Manufacturing Company) 1P6M 0.18 /spl mu/m CMOS process, with 1.8 V power supply, is employed to carry out the entire design. By taking advantage of the large current provided by low V/sub TH/ and low leakage provided by the high V/sub TH/, the threshold voltage of the wordline controlled NMOS transistors of memory cells are variable. When the cell is in the read or write mode, the V/sub TH/ of the wordline controlled NMOS transistors is pulled high such that the drain current is increased. By contrast, if it is idle in a standby mode, their bulk voltage is reduced by shorting their bulk to ground voltage. The proposed 4 Kb 6-T SRAM, by simulated measurement, is found to possess a 2.2 ns access time in the R/W mode, and consume 43.6 mW in the standby mode. The highest operating clock rate is 667 MHz.