HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems

This letter presents a toolchain called <italic>HotSniper</italic> developed by integrating <italic>HotSpot</italic> temperature modeling tool with <italic>Sniper</italic> many-core simulator. <italic>HotSniper</italic> allows for interval thermal simulation of many-cores, which is several times faster than the cycle-accurate many-core thermal simulations and at the same time is more accurate than trace-based many-core thermal simulations. <italic>HotSniper</italic> toolchain provides efficient means to perform thermal-aware hardware–software codesign of many-core processors in domain of embedded systems. The source code for <italic>HotSniper</italic> has been made public.

[1]  Somayeh Sardashti,et al.  The gem5 simulator , 2011, CARN.

[2]  Lieven Eeckhout,et al.  Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation , 2011, 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC).

[3]  Larry Rudolph,et al.  Metrics and Benchmarking for Parallel Job Scheduling , 1998, JSSPP.

[4]  Iraklis Anagnostopoulos,et al.  Performance-Aware Resource Management of Multi-Threaded Applications on Many-Core Systems , 2017, ACM Great Lakes Symposium on VLSI.

[5]  Arpad Gellert,et al.  Enhancing the Sniper simulator with thermal measurement , 2014, 2014 18th International Conference on System Theory, Control and Computing (ICSTCC).

[6]  Kevin Skadron,et al.  HotSpot: a dynamic compact thermal model at the processor-architecture level , 2003, Microelectron. J..

[7]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[8]  Lieven Eeckhout,et al.  Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads , 2011, 2011 IEEE International Symposium on Workload Characterization (IISWC).

[9]  Kai Li,et al.  The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).

[10]  Stijn Eyerman,et al.  Interval simulation: Raising the level of abstraction in architectural simulation , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[11]  Jörg Henkel,et al.  Invasive manycore architectures , 2012, 17th Asia and South Pacific Design Automation Conference.