A 19.2 GOPS mixed-signal filter with floating-gate adaptation

We have built a 48-tap, mixed-signal adaptive FIR filter with 8-bit digital input and an analog output with 10 bits of resolution. The filter stores its tap weights in nonvolatile analog memory cells using synapse transistors, and adapts using the least mean square (LMS) algorithm. We run the input through a digital tapped delay line, multiply the digital words with the analog tap weights using mixed-signal multipliers, and adapt the tap coefficients using pulse-based feedback. The accuracy of the weight updates exceeds 13 bits. The total die area is 2.6 mm/sup 2/ in a 0.35-/spl mu/m CMOS process. The filter delivers a performance of 19.2 GOPS at 200 MHz, and consumes 20 mW providing a 6-mA differential output current.

[1]  Paul E. Hasler,et al.  A high-resolution non-volatile analog memory cell , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[2]  Howard C. Card,et al.  Tolerance to analog hardware of on-chip learning in backpropagation networks , 1995, IEEE Trans. Neural Networks.

[3]  David Hsu,et al.  Learning Spike-Based Correlations and Conditional Probabilities in Silicon , 2001, NIPS.

[4]  Jie Zhu,et al.  Anti-Hebbian learning in topologically constrained linear networks: a tutorial , 1993, IEEE Trans. Neural Networks.

[5]  M. Lenzlinger,et al.  Fowler‐Nordheim Tunneling into Thermally Grown SiO2 , 1969 .

[6]  Bernard Widrow,et al.  Adaptive Signal Processing , 1985 .

[7]  Miguel Figueroa,et al.  Adaptive CMOS: from biological inspiration to systems-on-a-chip , 2002, Proc. IEEE.

[8]  Christopher J. Diorio,et al.  A mixed-signal approach to high-performance low-power linear filters , 2001, IEEE J. Solid State Circuits.

[9]  T. Yamasaki,et al.  A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[10]  Miguel Figueroa,et al.  Competitive learning with floating-gate circuits , 2002, IEEE Trans. Neural Networks.

[11]  Carver Mead,et al.  Analog VLSI and neural systems , 1989 .

[12]  Paul Hasler,et al.  An Autozeroing Floating-Gate Amplifier , 2001 .

[13]  Paul E. Hasler,et al.  Correlation learning rule in floating-gate pFET synapses , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[14]  C. Diorio,et al.  A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[15]  J.P. Keane,et al.  An adaptive analog noise-predictive decision-feedback equalizer , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[16]  Sergio Verdú,et al.  Linear multiuser detectors for synchronous code-division multiple-access channels , 1989, IEEE Trans. Inf. Theory.

[17]  Carver A. Mead,et al.  A Complementary Pair of Four-Terminal Silicon Synapses , 1997 .

[18]  Shu Wang,et al.  Blind adaptive multiuser detection , 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

[19]  K. Hara,et al.  A 23 mW 256-tap 8 MSample/s QPSK matched filter for DS-CDMA cellular telephony using recycling integrator correlators , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[20]  M.J.M. Pelgrom,et al.  Matching properties of MOS transistors , 1989 .

[21]  Eiji Takeda,et al.  Hot-Carrier Effects in MOS Devices , 1995 .