VLSI implementation of mod-p multipliers using homomorphisms and hybrid cellular automata

The VLSI implementation of mod-p multipliers, where p is prime, using homomorphisms and one-dimensional hybrid cellular automata (HCA) is presented. This new technique uses the maximum-length cycle produced by HCA, to realise implementation using the minimum possible number of cells in the array. A new theorem on homomorphisms shows how a cyclic group can be mapped into a state group of HCA, of smaller order, which can be implemented more simply than the original. The technique is demonstrated through the VLSI implementation of a modest, mod-127 multiplier. Significant reductions in silicon area, about 95%, are achieved relative to a previous approach that used two-dimensional cellular automata (CA). Layout of the mod-127 multiplier chip has been realised using dual-layer metal, 1.5 μm, n-well, CMOS technology from European Silicon Structures (ES2). Total silicon area is 1.2×0.8 mm2 comprising about 2100 transistors, and multiplication can be obtained up to a maximum clock frequency of 66 MHz. This approach is shown to be encouraging for implementing large devices in terms of silicon area but performance is disappointing. The work demonstrates the flexibility of the HCA array architecture, in terms of modularity, parallelism and local communications; it is particularly well suited for VLSI implementations.