STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs

In this paper the authors demonstrate the impact of the floorplan on the temperature-dependent leakage power of a system on chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. The authors implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation

[1]  Sani R. Nassif,et al.  Full chip leakage estimation considering power supply and temperature variations , 2003, ISLPED '03.

[2]  Kaustav Banerjee,et al.  A thermally-aware methodology for design-specific optimization of supply and threshold voltages in nanometer scale ICs , 2005, 2005 International Conference on Computer Design.

[3]  Fei Li,et al.  Microarchitecture level power and thermal simulation considering temperature dependent leakage model , 2003, ISLPED '03.

[4]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[5]  Kaushik Roy,et al.  Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[6]  Ieee Circuits,et al.  20th International Conference on VLSI Design : held jointly with 6th International Conference on Embedded Systems : proceedings : 6-10 January, 2007, Bangalore, India , 2007 .

[7]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[8]  Kevin Skadron,et al.  Control-theoretic techniques and thermal-RC modeling for accurate and localized dynamic thermal management , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.

[9]  Kevin Skadron,et al.  Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  C. P. Ravikumar,et al.  Leakage power estimation for deep submicron circuits in an ASIC design environment , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.