Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.

[1]  Jaejin Lee,et al.  2-D Non-Isolated Pixel 6/8 Modulation Code , 2014, IEEE Transactions on Magnetics.

[2]  Horst Zimmermann,et al.  Monolithically integrated optical receiver with large-area avalanche photodiode in high-voltage CMOS technology , 2014 .

[3]  Minoru Watanabe,et al.  High-resolution configuration of optically reconfigurable gate arrays , 2015, 2015 International Symposium on Next-Generation Electronics (ISNE).

[4]  Minoru Watanabe,et al.  Mono-instruction set computer architecture on a 3D optically reconfigurable gate array , 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

[5]  P. Heremans,et al.  A monolithic optoelectronic receiver in standard 0.7-μm CMOS operating at 180 MHz and 176-fJ light input energy , 1997, IEEE Photonics Technology Letters.

[6]  F. Kobayashi,et al.  A dynamic differential reconfiguration circuit for optically differential reconfigurable gate arrays , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[7]  A. Emami-Neyestanak,et al.  CMOS transceiver with baud rate clock recovery for optical interconnects , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[8]  P.A. Mitkas,et al.  Smart photodetector array for page-oriented optical memory in 0.35-μm CMOS , 1998, IEEE Photonics Technology Letters.

[9]  Horst Zimmermann,et al.  PIN Photodiode Optoelectronic Integrated Receiver Used for 3-Gb/s Free-Space Optical Communication , 2014, IEEE Journal of Selected Topics in Quantum Electronics.

[10]  Horst Zimmermann,et al.  3 Gbit/s optical receiver IC with high sensitivity and large integrated pin photodiode , 2013 .

[11]  D. Kossives,et al.  Clocked-sense-amplifier-based smart-pixel optical receivers , 1996, IEEE Photonics Technology Letters.

[12]  Horst Zimmermann,et al.  Advanced photo integrated circuits in CMOS technology , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).

[13]  J.E. Roth,et al.  An Optical Interconnect Transceiver at 1550 nm Using Low-Voltage Electroabsorption Modulators Directly Integrated to CMOS , 2007, Journal of Lightwave Technology.

[14]  Clint L. Schow,et al.  35-Gb/s VCSEL-Based optical link using 32-nm SOI CMOS circuits , 2013, 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC).

[15]  Quan Pan,et al.  A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer , 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.