Correction of MEU Errors in AES Using Multi Bit Errors Correction Technique

Comprehensive design efforts are needed for implementing algorithms onto an embedded system, which generally have a low power and area budget as well as high throughput requirement. Another important criterion of such systems is fault resiliency, which help them to perform in a robust environment. The general motivation in this direction is to have the general purpose instructions to be taken care by the software, whereas specialized hardware blocks are used to accelerate the execution of complex blocks. It also serves as a good target for embedded applications due to availability of general purpose CPU as well as other needed functional blocks in form of soft cores and dedicated resources (hard cores). Radiation induced faults resulting to single event upsets (SEU) and multiple event upsets (MEU), intentional attacker etc. Though a good number of research work exists on detecting errors for crypto-hardware but very few works can found on error correction using hardware techniques. In this paper, we present a novel crypto-hardware design involving BCH error detection code.