Resistive Bridging Fault Simulation of Industrial Circuits

We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number of faults to be simulated compared with stuck-at fault simulation.

[1]  D. M. H. Walker,et al.  Accurate fault modeling and fault simulation of resistive bridges , 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

[2]  Michel Renovell,et al.  CMOS bridging fault modeling , 1994, Proceedings of IEEE VLSI Test Symposium.

[3]  Susmita Sur-Kolay,et al.  Test pattern generation for power supply droop faults , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[4]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Wojciech Maly,et al.  From Contamination to Defects, Faults and Yield Loss , 1996 .

[6]  D. M. H. Walker,et al.  Resistive bridge fault modeling, simulation and test generation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[7]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[8]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[9]  Weiping Shi,et al.  A circuit level fault model for resistive bridges , 2003, TODE.

[10]  Yuyun Liao,et al.  Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[11]  D. M. H. Walker,et al.  PROBE: a PPSFP simulator for resistive bridging faults , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[12]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[13]  Janak H. Patel,et al.  E-PROOFS: A CMOS bridging fault simulator , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[14]  Mark Mohammad Tehranipoor,et al.  Pattern generation and estimation for power supply noise analysis , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[15]  Melvin A. Breuer,et al.  Test generation for ground bounce in internal logic circuitry , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[16]  Terumine Hayashi,et al.  Faulty resistance sectioning technique for resistive bridging fault ATPG systems , 2001, Proceedings 10th Asian Test Symposium.

[17]  Robert C. Aitken.  Finding defects with fault models , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[18]  Steven D. Millman,et al.  AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATOR , 1991, 1991, Proceedings. International Test Conference.

[19]  Tracy Larrabee,et al.  Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.

[20]  Tracy Larrabee,et al.  Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks , 1995, 32nd Design Automation Conference.

[21]  F. Joel Ferguson,et al.  Sandia National Labs , 2022 .

[22]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[23]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[24]  Michele Favalli,et al.  Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[25]  Michel Renovell,et al.  The concept of resistance interval: a new parametric model for realistic resistive bridging fault , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[26]  Jacob A. Abraham,et al.  A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[27]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[28]  Sreejit Chakravarty,et al.  A scalable and efficient methodology to extract two node bridges from large industrial circuits , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[29]  Kwang-Ting Cheng,et al.  Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Irith Pomeranz,et al.  Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits , 2004 .

[31]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[32]  M. Ray Mercer,et al.  REDO-random excitation and deterministic observation-first commercial experiment , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[33]  Bernd Becker,et al.  Automatic test pattern generation for resistive bridging faults , 2004, Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).

[34]  Florence Azaïs,et al.  Detection of Defects Using Fault Model Oriented Test Sequences , 1999, J. Electron. Test..

[35]  Sandip Kundu,et al.  Defect-Based Test : A Key Enabler for Successful Migration to Structural Test , 1999 .

[36]  Bernd Becker,et al.  SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges , 2007 .

[37]  Edward J. McCluskey,et al.  "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.

[38]  Bernd Becker,et al.  Simulating Resistive-Bridging and Stuck-At Faults , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.