Introduction to SRAM

The trend of Static Random Access Memory (SRAM) along with CMOS technology scaling in different processors and system-on-chip (SoC) products has fuelled the need of innovation in the area of SRAM design. SRAM bitcells are made of minimum geometry devices for high density and to keep the pace with CMOS technology scaling, as a result, they are the first to suffer from technology scaling induced side-effects. At the same time, success of next generation technology depends on the successful realization of SRAM. Therefore, different SRAM bitcell topologies and array architectures have been proposed in the recent past to meet the nano-regime challenges. Some of the major challenges in SRAM design includes poor stability, process variation tolerance, device degradation due to ageing and soft errors. In this chapter, introduction and importance of SRAM in memory hierarchy of a modern computer system and its peripheral circuitries have been presented. Different SRAM bitcell topologies and their merits and de-merits are also highlighted.

[1]  S. Natarajan,et al.  A high density, low leakage, 5T SRAM for embedded caches , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[2]  H. Kawaguchi,et al.  A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[3]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[4]  Richard F. Hobson,et al.  A New Single-Ended SRAM Cell With Write-Assist , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Magdy A. Bayoumi,et al.  Low-Power Cache Design Using 7T SRAM Cell , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  T. Fukai,et al.  Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies , 2007, 2007 IEEE International Electron Devices Meeting.

[7]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[8]  A. Chandrakasan,et al.  A 180-mV subthreshold FFT processor using a minimum energy design methodology , 2005, IEEE Journal of Solid-State Circuits.

[9]  Bo Zhai,et al.  A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM , 2008, IEEE Journal of Solid-State Circuits.

[10]  K. Takeda,et al.  A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[11]  K. Roy,et al.  A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM , 2007, IEEE Journal of Solid-State Circuits.

[12]  Andreas Moshovos,et al.  Low-leakage asymmetric-cell SRAM , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[13]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[14]  Massoud Pedram,et al.  Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[15]  K. Ishibashi,et al.  A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits , 2007, IEEE Journal of Solid-State Circuits.

[16]  H. Shinohara,et al.  A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM , 1983, IEEE Journal of Solid-State Circuits.

[17]  Naveen Verma,et al.  Design considerations for ultra-low energy wireless microsensor nodes , 2005, IEEE Transactions on Computers.

[18]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.

[19]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[20]  A.P. Chandrakasan,et al.  A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation , 2007, IEEE Journal of Solid-State Circuits.

[21]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Seongsoo Lee,et al.  Run-time voltage hopping for low-power real-time systems , 2000, DAC.

[23]  K. Anami,et al.  A 20 ns 4 Mb CMOS SRAM with hierarchical word decoding architecture , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[24]  H. Yamauchi,et al.  A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses , 2008, IEEE Journal of Solid-State Circuits.

[25]  H. Yamauchi,et al.  A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme , 2006, IEEE Journal of Solid-State Circuits.

[26]  Nomura Masahiro,et al.  A Read-Static-Noise-Margin-Free SRAM cell for low-Vdd and High-speed applications , 2005 .

[27]  Kaushik Roy,et al.  Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits , 2005 .

[28]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[29]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[30]  Chia-Hsiung Kao,et al.  Single-ended SRAM with high test coverage and short test time , 2000, IEEE Journal of Solid-State Circuits.

[31]  C.H. Kim,et al.  A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing , 2008, IEEE Journal of Solid-State Circuits.

[32]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..