The High performance Multiplexer based Adder Circuits

The need for extending low power circuits increased with the advent of use of large number of portable devices like cell phones, calculators, miniature computers etc. In all these devices, a long battery life is desired. An increase in battery life can be achieved by reducing power consumption of individual circuits. One of the methods to reduce the power consumption is by operating the devices at low current and low voltages. Operating the devices below threshold voltages is called as sub-threshold operation and the region of operation is called sub-threshold region. In this region, leakage current is used as operating current and power consumption is reduced significantly. The paper mainly focuses on the operation of various High performance Multiplexer based digital 1-bit Adder circuits[1] in sub-threshold region. The reduction in average power when compared to their super-threshold operation is analyzed. The variation of performance parameters and limitation of frequency of operation with variation in supply voltage are investigated. By varying the supply voltage below the threshold voltage, power can be reduced considerably. All the investigations in the paper are carried out using H-spice simulation tool. The circuits used are of 65nm process technology.