A New VLSI Architecture for Turbo Decoder Employing De-interleaver Table Free Method

This paper presents a new interleaver and de- interleaver VLSI architecture for turbo decoder. In our design, we propose a novel interleaving method, called de- interleaver table free, which uses only the interleaver table to perform interleaver and de-interleaver. With this improved methodology, we can use only half size of two-port RAM to implement, as extrinsic memory will read and write in same sequence. This new architecture can remove de-interleaver table and provide 50% of extrinsic memory bits reducing. Finally, we have designed a turbo decoder with TSMC 0.18 mum 1P6M technology for demonstrating the architecture of the de- interleaver table free. The chip occupies 1.8 x 1.8 mm2 , consumes 54.64 mW and supports 13.03 Mbps decoding speed in 6 times of iteration.