Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise

Application of the structural methodology to the LDO design creates a new class of circuits: any load stable, with instant transient response, large power supply rejection and low noise. Presented are examples of the embedded in SoC LDOs for the SRAM unit (5 ns reaction time on the load steps), radio transmitter (shaping the required noise vs. frequency curve) and for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process.