论文信息 - Low-power, wide-range time-to-digital converter for all digital phase-locked loops

Low-power, wide-range time-to-digital converter for all digital phase-locked loops

A time-to-digital converter (TDC) for a low-power, wide-range all digital phase-locked loop (ADPLL) is presented. The proposed TDC uses an enabling signal with variable duration to achieve low power and wide range. For verification purpose, the ADPLL is fabricated in a 0.11 µm CMOS technology. The ADPLL dissipates 6.02mW at an output frequency of 1.68GHz and its output frequency is measured as 0.24–1.68 GHz from a 1.2 V supply.

Soo-Won Kim | In-Chul Hwang | Chan-Hui Jeong | Chan-Keun Kwon | H. Kim

[1] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[2] A.A. Abidi,et al. A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution , 2009, IEEE Journal of Solid-State Circuits.

[3] Poras T. Balsara,et al. 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4] Tadashi Maeda,et al. A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter , 2010, IEEE Journal of Solid-State Circuits.