A Novel Latch Circuit against Single Event Upset

Due to the scaling of CMOS technology dimension, the occurrence of transient fault will be increased when the sensitive nodes are struck by high-energy neutrons and alpha particles. If the transient fault affects and changes the value of the nodes of a sequential element, it will cause single event upset (SEU). To overcome this problem, a reliable latch is proposed to protect both internal and output nodes in this paper. The simulation results of TSMC 28nm CMOS logic process show that the latch has good anti SEU, low power consumption and high-speed performance.

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