Automated analysis of timing faults in synchronous MOS circuits

The application of the SLOCOP timing verifier, which uses a rule-based subcircuit partitioning, is considered. The rule-based method is used to transform the network of MOS transistors, obtained from the physical layout by extraction into a network of unidirectional subcircuits. Each subcircuit is characterized by a logic model, which is used to accurately derive the timing constraints. The timing model of the circuit, required by this algorithm, is derived from the created subcircuit structure. The logic model makes it possible to eliminate false edges in the signal propagation graph. The resulting timing verifier can be used for a wide range of static and dynamic nMOS and CMOS circuits.<<ETX>>

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