Performance Analysis and Implementation of CMOS Current Starved Voltage Controlled Oscillator for Phase Locked Loop

The work is based on Current Starved Voltage controlled oscillator (CSVCO) for a Phase Locked Loop (PLL) in 180 nm process. Phase locked loop's were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existing generation, there has to be quick development with the technique. In most of the application PLL's were used for clock and data recovery purpose, from that perspective jitter will stand as a huge problem for the designers. The main aim of this thesis was to design a Current Starved Voltage controlled oscillator (CSVCO) that should bring down the jitter as down as possible which was designed as standalone; the designed CSVCO would be later placed in a PLL. To understand the concept and problem about jitter at the early stage of the project, an Analog PLL was designed in block level and tested for different types of jitter and then design of a CSVCO was started. This document was about the design of a Current Starved Voltage controlled oscillator which operates with the center frequency of 1.25 GHz. This project work describes the design and simulation of miscellaneous blocks of an PLL for the 3.33 GHz band. The reference frequency is 500 MHz and the Current Starved Voltage controlled oscillator output frequency is 1.25 GHz to 3.33 GHz in a state-of the-art 180nm process, with 1 V supply voltage.

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