论文信息 - A 0.35 /spl mu/m CMOS 4.8 Gb/s 4:1 multiplexer

A 0.35 /spl mu/m CMOS 4.8 Gb/s 4:1 multiplexer

A 4.8 Gbit/s 4:1 multiplexer was designed in source coupled logic and fabricated in 0.35 /spl mu/m CMOS technology. It has a power dissipation of less than 1W from a 5V supply and a size of 1/spl times/1.05 mm/sup 2/, and can be directly applied to an optical fiber link at STM-16 (2.488 Gbit/s) level of synchronous digital hierarchy (SDH).

[1] Shizhong Xie,et al. CMOS limiting amplifier for SDH STM-16 optical receiver , 2001 .

[2] Shoichi Shimizu,et al. A 10ghz Gaas 8b Multiplexer/demultiplexer Chip Set For The Sonet Sts-192 System , 1991 .

[3] Tetsuo Endoh,et al. 0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation , 2001, IEEE J. Solid State Circuits.