Processing mechanics for flip-chip assemblies

Abstract In this paper, a non-linear finite element framework has been implemented to simulate the sequential build-up of a flip-chip package. A generalized deformation model with element removal and addition is used to activate and deactivate the underfill material layer to simulate flip-chip package fabrication. Using process models, one can determine the warpage stresses at any intermediate stage in the process. In addition, topological change is also considered in order to model the sequential steps during the flip-chip assembly. Geometric and material nonlinearity which includes the creep behavior of underfill and solder balls, and temperature-dependent material properties are considered. Different stress-free temperatures for different elements in the same model are used to simulate practical manufacturing process-induced thermal residual stress field in the chip assembly. This approach (the processing model established in this paper) is in contrast to the non-processing model employed by many researchers, which is shown to yield overly conservative and sometimes erroneous results, leading to non-optimal design solutions. From the finite element analysis, it is found that the strains and deflections obtained from the non-processing model are generally smaller than those obtained from the processing model due to the negligence of the bonding process-induced residual strains and warpage. Furthermore, the fatigue life for the outmost solder ball predicted by the processing model is much shorter than that predicted by the non processing model based on the Coffin–Manson equation. On the other hand, in order to prove the soundness of the framework established in this paper, the test results obtained by using the laser moireinterferometry technique are compared with the results achieved from the proposed numerical analysis vehicle. It is shown that the deformation values of the flip-chip package predicted from the finite element analysis are in a good agreement with those obtained from the test.

[1]  Sheng Liu,et al.  Bimaterial interfacial crack growth as a function of mode-mixity , 1995 .

[2]  S. Liu,et al.  An investigation to popcorning mechanisms for IC plastic packages : EMC cracking , 1997 .

[3]  Arturo Cifuentes,et al.  Some Modeling Issues on the Finite Element Computation of Thermal Stresses in Metal Lines , 1993 .

[4]  H. D. Solomon,et al.  Low Cycle Fatigue , 1988 .

[5]  Arturo Cifuentes,et al.  Modeling of multilevel structures: a general method for analyzing stress evolution during processing , 1992 .

[6]  Jianjun Wang,et al.  Investigation of Interfacial Fracture Behavior of a Flip-Chip Package Under a Constant Concentrated Load , 1997, Application of Fracture Mechanics in Electronic Packaging.

[7]  P. Ifju,et al.  High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials , 1995 .

[8]  Sheng Liu,et al.  Behavior of delaminated plastic IC packages subjected to encapsulation cooling, moisture absorption, and wave soldering , 1995 .

[9]  Zhengfang Qian,et al.  Visco-elastic-plastic properties and constitutive modeling of underfills , 1999 .

[10]  H. Saunders.  Book Reviews : NUMERICAL METHODS IN FINITE ELEMENT ANALYSIS K.-J. Bathe and E.L. Wilson Prentice-Hall, Inc, Englewood Cliffs, NJ , 1978 .

[11]  Jian Yang,et al.  Visco-elastic-plastic properties and constitutive modeling of underfills , 1998, 1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206).

[12]  Yifan Guo,et al.  Solder Ball Connect (SBC) assemblies under thermal loading: I. Deformation measurement via moiré interferometry, and its interpretation , 1993, IBM J. Res. Dev..

[13]  K. Bathe.  Finite Element Procedures , 1995 .

[14]  Sheng Liu,et al.  CTE-measurement and delamination growth by a real time Moire technique , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.