Computer-aided design for VLSI circuit manufacturability
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[1] Andrzej J. Strojwas,et al. Design for Manufacturability and Yield , 1989, 26th ACM/IEEE Design Automation Conference.
[2] Ping Yang,et al. SIERRA: a 3-D device simulator for reliability modeling , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Wojciech Maly. Feasibility of Large Area Integrated Circuits , 1989 .
[4] Wojciech Maly,et al. Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[5] Wojciech Maly,et al. Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[6] Wojciech Maly,et al. Current sensing for built-in testing of CMOS circuits , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[7] C. Kooperberg,et al. Circuit layout and yield , 1988, IEEE J. Solid State Circuits.
[8] Wojciech Maly,et al. A circuit breaker for redundant IC systems , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
[9] Andrzej J. Strojwas,et al. Statistical process simulation for CAD/CAM , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.
[10] A. J. Strojwas. The process engineer's workbench , 1988 .
[11] Siegfried Selberherr,et al. Two-dimensional modeling of ion implantation induced point defects , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Robert W. Dutton,et al. The efficient simulation of coupled point defect and impurity diffusion , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[13] Francisco A. Leon. Numerical modeling of glass flow and spin-on planarization , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] Robert W. Dutton,et al. Methodology for submicron device model development , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Bruno Riccò,et al. MOS2: an efficient MOnte Carlo Simulator for MOS devices , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] Andrzej J. Strojwas,et al. A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Randal E. Bryant,et al. Boolean Analysis of MOS Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[18] Hiroo Masuda,et al. A Two-Dimensional Integrated Process Simulator: SPIRIT-I , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] D. M. H. Walker,et al. VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[20] C. Stapper. Yield statistics for large area ICs , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[21] Charles F. Hawkins,et al. Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs , 1986, ITC.
[22] J. P. Spoto,et al. Statistical Integrated Circuit Design and Characterization , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[23] Andrzej J. Strojwas. The CMU-CAM System , 1985, IEEE Design & Test of Computers.
[24] Charles L. Wilson,et al. Accurate current calculation in two-dimensional MOSFET models , 1985, IEEE Transactions on Electron Devices.
[25] Randolph E. Bank,et al. Transient simulation of silicon devices and circuits , 1985, IEEE Transactions on Electron Devices.
[26] Siegfried Selberherr,et al. Simulation of critical IC-fabrication steps , 1985, IEEE Transactions on Electron Devices.
[27] K. Lee,et al. SIMPL-2 (SIMulated Profiles from the Layout-Version 2) , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.
[28] E. A. Valsamakis. Generator for a custom statistical bipolar transistor model , 1985 .
[29] C. Stapper. The effects of wafer to wafer defect density variations on integrated circuit defect and fault distributions , 1985 .
[30] Andrzej J. Strojwas,et al. A Pattern Recognition Based Method for IC Failure Analysis , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[31] Y. Aoki,et al. CASTAM: A process variation analysis simulator for MOS LSI's , 1984, IEEE Transactions on Electron Devices.
[32] Charles H. Stapper,et al. Modeling of Defects in Integrated Circuit Photolithographic Patterns , 1984, IBM J. Res. Dev..
[33] Robert W. Atherton. The Application of Control Theory to the Automation of I.C. Manufacturing: Progress and Problems , 1984, 1984 American Control Conference.
[34] Randal E. Bryant,et al. A Switch-Level Model and Simulator for MOS Digital Systems , 1984, IEEE Transactions on Computers.
[35] S. Selberherr. Analysis and simulation of semiconductor devices , 1984 .
[36] Sani R. Nassif,et al. FABRICS II: A Statistically Based IC Fabrication Process Simulator , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[37] T. W. Griswold,et al. Pinhole array capacitor for oxide integrity analysis , 1983 .
[38] D.L. Scharfetter,et al. General optimization and extraction of IC device model parameters , 1983, IEEE Transactions on Electron Devices.
[39] H. H. Hansen,et al. FEDSS—Finite-element diffusion-simulation system , 1983, IEEE Transactions on Electron Devices.
[40] John M. Acken. Testing for Bridging Faults (Shorts) in CMOS Circuits , 1983, 20th Design Automation Conference Proceedings.
[41] Michael A. Wesley,et al. OYSTER: A Study of Integrated Circuits as Three Dimensional Structures , 1983, IBM J. Res. Dev..
[42] Ping Yang,et al. STATISTICAL MODELING FOR EFFICIENT PARAMETRIC YIELD ESTIMATION , 1983 .
[43] A.R. Neureuther,et al. IC process modeling and topography design , 1983, Proceedings of the IEEE.
[44] K. Doganis,et al. Optimized Extraction of MOS Model Parameters , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[45] Andrzej J. Strojwas,et al. Statistical Simulation of the IC Manufacturing Process , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[46] D.W. Greve,et al. Programming mechanism of polysilicon resistor fuses , 1982, IEEE Transactions on Electron Devices.
[47] K. Antreich,et al. Design centering by yield prediction , 1982 .
[48] K. Singhal,et al. Statistical design centering and tolerancing using parametric sampling , 1981 .
[49] Andrzej J. Strojwas,et al. Fabrication based statistical design of monolithic IC's , 1981 .
[50] B. Penumalli,et al. Process simulation in two dimensions , 1981, 1981 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[51] Martin G. Buehler. The Use of Electrical Test Structure Arrays for Integrated Circuit Process Evaluation , 1980 .
[52] S. Selberherr,et al. MINIMOS - A Two-Dimensional MOS Transistor Analyzer , 1980, IEEE Journal of Solid-State Circuits.
[53] H. Ryssel,et al. Simulation of doping processes , 1980, IEEE Transactions on Electron Devices.
[54] K. S. Tahim,et al. A radial exploration approach to manufacturing yield estimation and design centering , 1979 .
[55] R.P. Cenker,et al. A fault-tolerant 64K dynamic random-access memory , 1979, IEEE Transactions on Electron Devices.
[56] R. Dutton,et al. Models for computer simulation of complete IC fabrication process , 1979, IEEE Transactions on Electron Devices.
[57] A. Neureuther,et al. A general simulator for VLSI lithography and etching processes: Part I—Application to projection lithography , 1979, IEEE Transactions on Electron Devices.
[58] Bruno O. Shubert,et al. Random variables and stochastic processes , 1979 .
[59] J. Bandler,et al. Optimal centering, tolerancing, and yield determination via updated approximations and cuts , 1978 .
[60] J. Bernard. The IC yield problem: A tentative analysis for MOS/SOS circuits , 1978, IEEE Transactions on Electron Devices.
[61] R.W. Dutton,et al. Correlation of fabrication process and electrical device parameter variations , 1977, 1976 International Electron Devices Meeting.
[62] C.P. Wu,et al. Redistribution of ion-implanted impurities in silicon during diffusion in oxidizing ambients , 1976, IEEE Transactions on Electron Devices.
[63] John W. Bandler,et al. Worst Case Network Tolerance Optimization , 1975 .
[64] R. M. Warner. Applying a composite model to the IC yield problem , 1974 .
[65] J. Prince,et al. Diffusion of Boron from Implanted Sources under Oxidizing Conditions , 1974 .
[66] John W. Bandler,et al. Optimization Methods for Computer-Aided Design , 1969 .
[67] J. W. Lathrop,et al. A discretionary wiring system as the interface between design automation and semiconductor array manufacture , 1967 .
[68] B. T. Murphy,et al. Cost-size optima of monolithic integrated circuits , 1964 .
[69] R. R. O'Brien,et al. A Statistical Approach to the Design of Diffused Junction Transistors , 1964, IBM J. Res. Dev..
[70] D. R. Cox,et al. Planning of Experiments , 1959 .