PLD-Based Design Guidelines

This chapter describes the design guidelines for ASIC and FPGA designs. The coding and design guidelines are useful in the RTL design cycle and recommended to be used for the efficient performance of the design. The design guidelines such as resource sharing, pipelining, logic duplications, grouping, use of signals and variables, gated clock, and clock enable logic are discussed in this chapter. Designers are requested to use these guidelines for area, speed, and power improvement in the design.