Synthesis of synchronous elastic architectures

A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, fine-granularity elasticity can be introduced at the level of functional units (e.g. ALUs, memories). A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented. The opportunities this protocol opens for microarchitectural design are discussed

[1]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[2]  Kenneth L. McMillan,et al.  Verification of Infinite State Systems by Compositional Model Checking , 1999, CHARME.

[3]  Pradip Bose,et al.  Synchronous interlocked pipelines , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[4]  Luca Benini,et al.  Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting , 1999, IEEE Trans. Computers.

[5]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[6]  Alberto L. Sangiovanni-Vincentelli,et al.  Coping with Latency in SOC Design , 2002, IEEE Micro.

[7]  Sandeep K. Shukla,et al.  Presentation and Formal Verification of a Family of Protocols for Latency Insensitive Design , 2005 .

[8]  Cheng-Kok Koh,et al.  Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels , 2003, ICCAD 2003.

[9]  Steven M. Nowick,et al.  Robust interfaces for mixed-timing systems , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Alberto L. Sangiovanni-Vincentelli,et al.  Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Fred Kröger,et al.  Temporal Logic of Programs , 1987, EATCS Monographs on Theoretical Computer Science.

[12]  Jean-Christophe Le Lann,et al.  POLYCHRONY for System Design , 2003, J. Circuits Syst. Comput..

[13]  Victor Varshavsky,et al.  GALA (Globally Asynchronous - Locally Arbitrary) Design , 2002, Concurrency and Hardware Design.

[14]  David L. Dill,et al.  Polynomial-time techniques for approximate timing analysis of asynchronous systems , 1998 .

[15]  Alberto L. Sangiovanni-Vincentelli,et al.  Combining retiming and recycling to optimize the performance of synchronous circuits , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..

[16]  Madhav P. Desai,et al.  A novel technique towards eliminating the global clock in VLSI circuits , 2004, 17th International Conference on VLSI Design. Proceedings..

[17]  Luciano Lavagno,et al.  Handshake protocols for de-synchronization , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..