Design and analysis of a dual gate tunnel FET with InGaAs source pockets for improved performance

[1]  V. N. Ramakrishnan,et al.  Performance Analysis of Germanium-Silicon Vertical Tunnel Field-Effect Transistors (Ge-Si-VTFETs) for Analog/RF Applications , 2022, Silicon.

[2]  S. Sridevi,et al.  InGaAs-Si Double Pocket-Dual Gate Tunnel FET Based 7T SRAM Design , 2022, Silicon.

[3]  P. Singh,et al.  III-V/Si staggered heterojunction based source-pocket engineered vertical TFETs for low power applications , 2020 .

[4]  Balraj Singh,et al.  Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance , 2020, IEEE Transactions on Electron Devices.

[5]  Satyabrata Jit,et al.  Device and Circuit-Level Assessment of GaSb/Si Heterojunction Vertical Tunnel-FET for Low-Power Applications , 2020, IEEE Transactions on Electron Devices.

[6]  Seungho Kim,et al.  Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches , 2020, Nature Nanotechnology.

[7]  Sridevi Sriadibhatla,et al.  Dual-chirality GAA-CNTFET-based SCPF-TCAM cell design for low power and high performance , 2019, Journal of Computational Electronics.

[8]  M. Hasan,et al.  TFET-Based Robust 7T SRAM Cell for Low Power Application , 2019, IEEE Transactions on Electron Devices.

[9]  J. Schulze,et al.  Enhancement of Ge-based p-channel vertical FET performance by channel engineering using planar doping and a Ge/SixGe1–x–ySny heterostructure model for low power FET applications , 2018, Semiconductor Science and Technology.

[10]  M. Pala,et al.  Vertical GaSb/AlSb/InAs Heterojunction Tunnel-FETs: A Full Quantum Study , 2018, IEEE Transactions on Electron Devices.

[11]  C. Pandey,et al.  Impact of Dielectric Pocket on Analog and High-Frequency Performances of Cylindrical Gate-All-Around Tunnel FETs , 2018 .

[12]  S. S. Chauhan,et al.  Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation , 2018 .

[13]  S. Loan,et al.  A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets , 2018, IEEE Transactions on Electron Devices.

[14]  Mehdi Saremi,et al.  A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance , 2017, IEEE Transactions on Electron Devices.

[15]  Dheeraj Sharma,et al.  Design and Analysis of Polarity Controlled Electrically Doped Tunnel FET With Bandgap Engineering for Analog/RF Applications , 2017, IEEE Transactions on Electron Devices.

[16]  Rita Rooyackers,et al.  Study of line-TFET analog performance comparing with other TFET and MOSFET architectures , 2017 .

[17]  Jaydeep P. Kulkarni,et al.  Source-Underlapped GaSb–InAs TFETs With Applications to Gain Cell Embedded DRAMs , 2016, IEEE Transactions on Electron Devices.

[18]  R. Rooyackers,et al.  Low-Frequency Noise Analysis and Modeling in Vertical Tunnel FETs With Ge Source , 2016, IEEE Transactions on Electron Devices.

[19]  Mamidala Jagadesh Kumar,et al.  In-Built N+ Pocket p-n-p-n Tunnel Field-Effect Transistor , 2014, IEEE Electron Device Letters.

[20]  Rakhi Narang,et al.  Drain current model for a gate all around (GAA) p-n-p-n tunnel FET , 2013, Microelectron. J..

[21]  J. Fastenau,et al.  Barrier-Engineered Arsenide–Antimonide Heterojunction Tunnel FETs With Enhanced Drive Current , 2012, IEEE Electron Device Letters.

[22]  O. Faynot,et al.  Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[23]  T. Fukui,et al.  Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[24]  Adrian M. Ionescu,et al.  Tunnel field-effect transistors as energy-efficient electronic switches , 2011, Nature.

[25]  Qin Zhang,et al.  Low-Voltage Tunnel Transistors for Beyond CMOS Logic , 2010, Proceedings of the IEEE.

[26]  T. Mayer,et al.  Temperature-Dependent – Characteristics of a Vertical Tunnel FET , 2010 .

[27]  K. Cheung.  On the 60 mV/dec @300 K limit for MOSFET subthreshold swing , 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

[28]  S. Datta,et al.  Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation , 2009, IEEE Transactions on Electron Devices.

[29]  Y. Yeo,et al.  Tunneling Field-Effect Transistor: Effect of Strain and Temperature on Tunneling Current , 2009, IEEE Electron Device Letters.

[30]  O. Rozeau,et al.  Analog/RF Performance of Multichannel SOI MOSFET , 2009, IEEE Transactions on Electron Devices.

[31]  K. Saraswat,et al.  Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope , 2008, 2008 IEEE International Electron Devices Meeting.

[32]  Chun-Huat Heng,et al.  A Variational Approach to the Two-Dimensional Nonlinear Poisson's Equation for the Modeling of Tunneling Transistors , 2008, IEEE Electron Device Letters.

[33]  Adrian M. Ionescu,et al.  A new definition of threshold voltage in Tunnel FETs , 2008 .

[34]  J.C.S. Woo,et al.  The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor , 2008, IEEE Transactions on Electron Devices.

[35]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[36]  M. Sakuraba,et al.  Thermal effect on strain relaxation in Ge films epitaxially grown on Si(100) using ECR plasma CVD , 2006 .

[37]  O. Faynot,et al.  Agglomeration control during the selective epitaxial growth of Si raised sources and drains on ultra-thin silicon-on-insulator substrates , 2005 .

[38]  Alok Naugarhiya,et al.  RF & linearity distortion sensitivity analysis of DMG-DG-Ge pocket TFET with hetero dielectric , 2021, Microelectron. J..

[39]  M. Aarthy,et al.  Design and Analysis Of An Ultra-L ow Power Single Electron Transistor Based Binary Multiplier , 2019 .

[40]  J. Woo,et al.  Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor , 2011, IEEE Transactions on Electron Devices.