High-performance low-power microprocessor circuits

approved: Shih-Lien Lu This thesis will discuss two critical components of a digital system -domino logic styles and flip-flops. In today's microprocessors, both domino logic and flip-flops are essential to high-performance and low-power design. Two new domino logic styles are presented and analyzed, Double Edge Triggered (DET) and Double Data Rate (DDR) Domino. Using a CMOS 0.25p.rn MOSIS model, HSPICE simulations show that a DET & DDR 8-bit adder has a maximum throughput of l.6Gops (Giga Operations per second) and 2Gops, respectively, while a conventional domino adder has only iGops. In addition, this thesis proposes a novel master-slave flip-flop. This flip-flop is compared with other known flip-flop structures. Using a CMOS 0.35j.tm MOSIS model, the new flipflop was simulated to have an optimal power-delay product. The proposed flip-flop consumes very low power, while having a very small clock load and data load. Redacted for Privacy Copyright by Steven K. Hsu

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