Transistor reliability characterization and modeling of the 22FFL FinFET technology

This paper describes the transistor reliability of Intel's 22FFL FinFET technology, which includes an extensive variety of device offerings to enable high performance and low power design options. Detailed evaluations of BTI, TDDB, self-heating, and HCI are included to demonstrate the impact from the various device's pitch, channel length, and threshold voltage. Process integration details are included to highlight the interaction with reliability mechanisms. In addition, modeling results are shown to be well matched to silicon on both discrete devices and benchmark circuits.

[1]  G. Curello,et al.  A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications , 2012, 2012 International Electron Devices Meeting.

[2]  A. Rahman,et al.  Reliability studies of a 22nm SoC platform technology featuring 3-D tri-gate, optimized for ultra low power, high performance and high density application , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[3]  S. Ramey,et al.  Transistor reliability variation correlation to threshold voltage , 2015, 2015 IEEE International Reliability Physics Symposium.

[4]  Chetan Prasad.  Advanced CMOS reliability challenges , 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

[5]  S. Mudanai,et al.  22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[6]  Karl Hess,et al.  Magnitude of the threshold energy for hot electron damage in metal–oxide–semiconductor field effect transistors by hydrogen desorption , 1999 .

[7]  S. Natarajan,et al.  Self-heat reliability considerations on Intel's 22nm Tri-Gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[8]  M. Agostinelli,et al.  Transistor aging and reliability in 14nm tri-gate technology , 2015, 2015 IEEE International Reliability Physics Symposium.

[9]  A. Rahman,et al.  Intrinsic transistor reliability improvements from 22nm tri-gate technology , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[10]  C. Auth,et al.  A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors , 2012, 2012 Symposium on VLSI Technology (VLSIT).